This invention relates to a circuit arrangement for processing sampled analog electrical signals.
Our co-pending U.K. patent application Nos. 8721758 (PHB33385) and 8721759 (PHB33386), which correspond to U.S. Pat. Nos. 4,864,217 (9/5/89) and 4,866,368 (9/12/89) respectively, disclose a method of processing sampled analog electrical signals in which the electrical quantity manipulated is current. This method is referred to hereinafter as switched current signal processing and circuit arrangements using this method are referred to as switched current circuits. It is known, in switched capacitor circuits, to manipulate electrical charges to perform signal processing of sampled analog electrical signals. However, in order to manipulate the charges high quality linear capacitors are required and in MOS integrated circuits these are commonly fibricated using two polysilicon layers. The provision of two polysilicon layers is not a standard part of the CMOS processes usually used for LSI and VLSI digital circuits and it therefore makes the provision of circuits combining analog and digital signal processing on a single integrated circuit more difficult.
In addition, the capacitors required for the signal manipulation in switched capacitor circuits occupy a large area, which can be half or more of the total chip area. By using switched current circuits the processing and chip area problems may be mitigated. However, it has been found convenient to use current mirror circuits in the implementation of switched current circuits and at least in the simpler embodiments, these circuits require a unidirectional input current. Consequently if, as is usually the case, there is a requirement to process bidirectional input signals, it is necessary to add a bias current to the bidirectional input current to ensure that a unidirectional input current is available. However, it is then necessary to ensure that the bias current is not itself processed in the same manner as the bidirectional input current since it will then be difficult to separate it from the precessed signal current. This requires additional bias current sources at various positions in the processing circuitry having different current magnitudes. Consequently, error can occur due to the difficulty of producing accurately defined bias currents and, in particular, matching current sources which may be widely separated over the area of an LSI or VLSI chip.
Our copending U.S. application No. 286,600 (12/16/88), now U.S. Pat. No. 4,958,123, discloses a circuit arrangement for processing sampled analogue electrical signals with each sample being in the form of a current. The circuit arrangement comprises means for combining, in predetermined propertions, the input sample current in a present sample period with current(s) derived from input sample current(s) in one or more preceding sample periods, and means for deriving the processed output signal from the combined current produced by the combining means in successive sample periods. The circuit arrangement preferably is formed by a plurality of circuit modules, each circuit module having a current input for receiving a bidirectional input signal current and a current output for supplying a bidirectional output signal current, means for adding a bias current to the bidirectional input current to produce a unidirectional current for processing by the circuit module, and means for subtracting a suitable scaled bias current from the processed unidirectional current to produce current at the current output of the circuit module.
By constructing the circuit arrangement from a plurality of circuit modules, which can be designed to perform particular functions, such as current storage, current amplification, current addition or subtraction, current inversion, and transferring only signal currents between the circuit modules, large systems can be constructed without requiring accurately matched bias current sources at widely spaced locations on an integrated circuit substrate. Thus, a complex signal processing arrangement can be implemented using comparatively simple building block modules in which each module is capable of receiving and producing bidirectional currents even though within the module only unidirectional currents can be handled.
One of the circuit modules disclosed comprises a current memory module which is capable of reproducing at its output in one sampling period a scaled version of the current applied to its input in a previous sampling period.
In order to process signals in switched current circuits it is necessary to be able to store currents from one sampling period to the next so that sample currents occurring in different sample periods can be combined in a desired manner to perform a given signal processing function.
A current memory module disclosed in our copending U.S. application No. 286,600, now U.S. Pat. No. 4,958,123 (9/18/90), comprises a current input, a current output, first and second switches controlled by first and second non-overlapping clock signals, and first and second memory cells, wherein the current input is coupled to the first memory cell by means fo the first switch and the first memory cell is coupled to the second memory cell be means of the second switch. The output of the second memory cell is coupled to the current output. Each memory cell comprises a field effect transistor, having a capacitor connected between its gate and source electrodes, which forms an output branch of a current mirror circuit. The first and second switches are arranged to isolate the input and output branches of the current mirror circuits, the output branch of the first current mirror circuit being connected to the input branch of the second current mirror circuit. By storing a charge on a capacitor which causes the gate-source potential of the field effect transistor to be maintained when the driving source is removed, the current produced through the transistor by the driving source can be maintained by the charge on the capacitor. Of course, the effectiveness of the current maintenance depends on the input resistance of the transistor and the period during which the current is to be maintained. Consequently, this is one factor which limits the maximum sampling period.
Forming the current memory cells as current mirror circuits having their input and output branches isolated by a switch enables the input current to be accurately produced at the output and enables the capacitor to be charged to the correct potential to maintain the output current at the desired value.
A further circuit module disclosed in U.S. Pat. No. 4,958,123is an integrator circuit module which is capable of integrating a bidirectional current applied to its input. The integrator circuit module comprises a current memory module and a feedback loop between a stored current output and a summing arrangement so that a stored current can be added to each current input sample. The integrator module may be arranged to perform either lossy or lossless integration, for example, by appropriately chossing the current ratios of current mirror circuits forming or associated with the current memory cells. The integrator modules are useful in forming various filter sections which may be used to construct filters of any desired complexity.
Another circuit module which is disclosed in the aforesaid U.S. patent is a static module which is capable of producing at its output a scaled version of the current applied to its input. The static module may have a plurality of inputs by means of which a plurality of input currents may be applied to the static module to enable current addition or subtraction to be performed by the static module. The static module may perform a current inversion between, its input(s) and output(s).
The static modules allow functions of current gain, signal inversion, current addition, current subtraction, and `fan-out` to be performed.
One static module comprises a current scaling curcuit, the current scaling circuit comprising means for applying an input current to the input branch of a first current mirror circuit, means for applying a bias current to the input branch of the first current mirror circuit, means for feeding the current from the output branch of the first current mirror circuit to the input branch of a second current mirror circuit, means for feeding the current from the output branch of the second current mirror circuit to the output of the static module, and means for substracting a bias current so that the output current produced by the scaling circuit is a scaled version of the input current applied to the input of the scaling circuit.
Since the static module has its input connected to the input branch of a current mirror circuit, which input branch is commonly formed by a diode connected transistor, it is necessary to ensure that when that is so the current flows in the current conducting direction of the diode. The provision of a bias current which is added to the input current enables this condition to be achieved for values of input current within the designed range. It would be possible, if a current inversion were desired, to take the output from the output branch of the first current mirror circuit and subtract the bias current, or a multiplied version of the bias current if the first current mirror has a current multiplication factor, from the current in the output branch of the first current mirror circuit to produce the required output current of the static module.
In one embodiment the means for applying a bias current to the input branch of the first current mirror circuit may comprise a first current source and means for adding the current produced by the first current source to the input current, and the means for subtracting a bias current may comprise a second current source and a current summing junction to which the output current from the second current source and the output current from the output branch of the second current mirror are applied with appropriate polarity. The scaled output current is derived from the summing junction. The second current mirror circuit may have a plurality of outputs, the static module having a corresponding plurality of outputs, each output of the second current mirror circuit being coupled to a corresponding output of the static module. The means for subtracting the suitably scaled bias current may comprise a bias current source connected to the input of a further current mirror circuit having a number of outputs corresponding to the number of outputs of the second current mirror circuit, the output current(s) produced by the further current mirror circuit being substracted from the corresponding output current(s) of the second current mirror circuit. The static module may be arranged to produce at its output an inversion of the current applied to its input, the input of the static module being coupled to the input of the further current mirror circuit instead of to the input of the first current mirror circuit.
In a further embodiment the static module is arranged to subtract a first current from a second current and to have a first input for application of the second current which is coupled to the input of the first current mirror circuit, a second input for application of the first current which is coupled to the input of the further current mirror circuit, and one or more outputs which are coupled to respective output branches of the second current mirror circuit.
Further embodiments disclosed a static module which is arranged to process a differential input current and produce a differential output current. Such a static module comprises first and second inputs for receiving a differential input current, first and second outputs for producing a differential output current, means for coupling the first input to a first input of a first current summing means, means for coupling a first bias current source to a second input of the first current summing means, means for coupling the output of the first current summing means to the input branch of a first current mirror first input of a second current summing means, means for coupling a second bias current source to a second input of the second current summing means, means for coupling the output of the second current summing means to the input branch of a second current mirror circuit, means for coupling a first output branch of the first current mirror circuit to the input branch of a third current mirror circuit, means for coupling a first output branch of the second current mirror circuit to the input branch of a fourth current mirror circuit, means for coupling a second output branch of the first current mirror circuit to a first input of a third current summing means, means for coupling an output branch of the fourth current mirror circuit to a second input of the third current summing means, means for coupling the output of the third current summing means to the first output, means for coupling a second branch of the second current mirror circuit to a first input of a fourth current summing means, means for coupling an output branch of the third current mirror circuit to a second input of the fourth current summing means, and means for coupling the output of the fourth summing means to the second output.
The static module can be provided with a number of further differential outputs wherein each of the current mirror circuits has a corresponding number of further output branches each of which is connected to appropriate further summing nodes. The static module may also be provided with a number of further differential inputs, each further differential input being connected to a further input of the first and second summing nodes.
Our copending U.S. application No. 446,518 (12/4/89) discloses a bilinear integrator using switched current signal processing and can be used as a module in switched current circuits having the capability of accepting a bidirectional input current and producing a bidirectional output current. The bilinear integrator disclosed in constructed from current memory modules and static modules such as those disclosed in U.S Pat. No. 4,958,123.
Our copending U.S. application No. 446,821 (12/6/89) discloses circuit modules equivalent in function to those disclosed in U.S. Pat. No. 4,958,123 and U.S. application No. 446,518 in which the transistors which pass signal currents are all of the same polarity and enable a minimum supply voltage to be utilized.
The circuit modules disclosed in these copending applications all use current mirror circuits for current scaling and a modified current mirror circuit to enable the storage of currents. When a plurality of currents are summed into a node the mismatch between the input impedance of the input of current mirror circuits receiving the summed currents and the combined output impedances of the current mirror circuits providing the currents to be summed is not great enough to allow the current summing to take place with a high degree of accuracy.